dc.contributor.author |
Broich, R
|
|
dc.contributor.author |
Grobler, H
|
|
dc.date.accessioned |
2015-03-12T09:50:35Z |
|
dc.date.available |
2015-03-12T09:50:35Z |
|
dc.date.issued |
2014-10 |
|
dc.identifier.citation |
Broich, R and Grobler, H. 2014. Soft-core dataflow processor architecture optimised for radar signal processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34(1), pp 43-51 |
en_US |
dc.identifier.issn |
0278-0070 |
|
dc.identifier.uri |
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6928471
|
|
dc.identifier.uri |
http://hdl.handle.net/10204/7909
|
|
dc.description |
Copyright: 2014 IEEE. Due to copyright restrictions, the attached PDF file only contains the abstract of the full text item. For access to the full text item, please consult the publisher's website. |
en_US |
dc.description.abstract |
Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel softcore streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end DSP processor by an average factor of 14 over a range of typical operating parameters in a radar signal processor application. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IEEE |
en_US |
dc.relation.ispartofseries |
Workflow;13930 |
|
dc.subject |
Transport-based processors |
en_US |
dc.subject |
Signal processing architectures |
en_US |
dc.subject |
Soft-core processors |
en_US |
dc.subject |
Processor design methodology |
en_US |
dc.subject |
Radar signal processors |
en_US |
dc.subject |
Processor design methodology |
en_US |
dc.subject |
Streaming architecture |
en_US |
dc.subject |
Circular dataflows |
en_US |
dc.title |
Soft-core dataflow processor architecture optimised for radar signal processing: Article |
en_US |
dc.type |
Article |
en_US |
dc.identifier.apacitation |
Broich, R., & Grobler, H. (2014). Soft-core dataflow processor architecture optimised for radar signal processing: Article. http://hdl.handle.net/10204/7909 |
en_ZA |
dc.identifier.chicagocitation |
Broich, R, and H Grobler "Soft-core dataflow processor architecture optimised for radar signal processing: Article." (2014) http://hdl.handle.net/10204/7909 |
en_ZA |
dc.identifier.vancouvercitation |
Broich R, Grobler H. Soft-core dataflow processor architecture optimised for radar signal processing: Article. 2014; http://hdl.handle.net/10204/7909. |
en_ZA |
dc.identifier.ris |
TY - Article
AU - Broich, R
AU - Grobler, H
AB - Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel softcore streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end DSP processor by an average factor of 14 over a range of typical operating parameters in a radar signal processor application.
DA - 2014-10
DB - ResearchSpace
DP - CSIR
KW - Transport-based processors
KW - Signal processing architectures
KW - Soft-core processors
KW - Processor design methodology
KW - Radar signal processors
KW - Processor design methodology
KW - Streaming architecture
KW - Circular dataflows
LK - https://researchspace.csir.co.za
PY - 2014
SM - 0278-0070
T1 - Soft-core dataflow processor architecture optimised for radar signal processing: Article
TI - Soft-core dataflow processor architecture optimised for radar signal processing: Article
UR - http://hdl.handle.net/10204/7909
ER -
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en_ZA |