dc.contributor.author |
Broich, R
|
|
dc.date.accessioned |
2014-09-05T12:54:10Z |
|
dc.date.available |
2014-09-05T12:54:10Z |
|
dc.date.issued |
2013-12 |
|
dc.identifier.citation |
Broich, R. 2013. A soft-core processor architecture optimised for radar signal processing applications. Master thesis. University of Pretoria, Department of Electrical, Electronic and Computer Engineering |
en_US |
dc.identifier.uri |
http://hdl.handle.net/10204/7653
|
|
dc.description |
A thesis submitted to the Faculty of Engineering, Built Environment and Information Technology, University of Pretoria, in fulfillment of the requirements for the Master of Engineering |
en_US |
dc.description.abstract |
Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of functionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture, data and signal-flow characteristics of common radar signal processing algorithms are analysed. Each algorithm is broken down into signal processing and mathematical operations. The computational requirements are then evaluated using an abstract model of computation to determine the relative importance of each mathematical operation. Critical portions of the radar applications are identified for architecture selection and optimisation purposes. |
en_US |
dc.language.iso |
en |
en_US |
dc.relation.ispartofseries |
Workflow;13188 |
|
dc.subject |
DSP architecture |
en_US |
dc.subject |
FPGA architecture |
en_US |
dc.subject |
Pipelined processor |
en_US |
dc.subject |
Processor design |
en_US |
dc.subject |
Radar signal processor |
en_US |
dc.subject |
Signal-flow characteristics |
en_US |
dc.subject |
Soft-core DSP |
en_US |
dc.subject |
Soft-core processor |
en_US |
dc.subject |
Streaming processor |
en_US |
dc.subject |
Transport-based processor |
en_US |
dc.title |
A soft-core processor architecture optimised for radar signal processing applications |
en_US |
dc.type |
Report |
en_US |
dc.identifier.apacitation |
Broich, R. (2013). <i>A soft-core processor architecture optimised for radar signal processing applications</i> (Workflow;13188). Retrieved from http://hdl.handle.net/10204/7653 |
en_ZA |
dc.identifier.chicagocitation |
Broich, R <i>A soft-core processor architecture optimised for radar signal processing applications.</i> Workflow;13188. 2013. http://hdl.handle.net/10204/7653 |
en_ZA |
dc.identifier.vancouvercitation |
Broich R. A soft-core processor architecture optimised for radar signal processing applications. 2013 [cited yyyy month dd]. Available from: http://hdl.handle.net/10204/7653 |
en_ZA |
dc.identifier.ris |
TY - Report
AU - Broich, R
AB - Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of functionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture, data and signal-flow characteristics of common radar signal processing algorithms are analysed. Each algorithm is broken down into signal processing and mathematical operations. The computational requirements are then evaluated using an abstract model of computation to determine the relative importance of each mathematical operation. Critical portions of the radar applications are identified for architecture selection and optimisation purposes.
DA - 2013-12
DB - ResearchSpace
DP - CSIR
KW - DSP architecture
KW - FPGA architecture
KW - Pipelined processor
KW - Processor design
KW - Radar signal processor
KW - Signal-flow characteristics
KW - Soft-core DSP
KW - Soft-core processor
KW - Streaming processor
KW - Transport-based processor
LK - https://researchspace.csir.co.za
PY - 2013
T1 - A soft-core processor architecture optimised for radar signal processing applications
TI - A soft-core processor architecture optimised for radar signal processing applications
UR - http://hdl.handle.net/10204/7653
ER -
|
en_ZA |