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Analysis of the computational requirements of a pulse-doppler radar signal processor

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dc.contributor.author Broich, R
dc.contributor.author Grobler, H
dc.date.accessioned 2012-07-26T10:40:05Z
dc.date.available 2012-07-26T10:40:05Z
dc.date.issued 2012-05
dc.identifier.citation Broich, R and Grobler, H. Analysis of the computational requirements of a pulse-doppler radar signal processor. 2012 IEEE Radar Conference, Atlanta, Georgia, USA, 7-11 May 2012, pp 0835-0840 en_US
dc.identifier.isbn 978-1-4673-0656-0
dc.identifier.uri http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6212253&tag=1
dc.identifier.uri http://hdl.handle.net/10204/6008
dc.description Copyright: 2012 IEEE. This is the post-print version of the paper. Reprinted, with permission, from Broich, R and Grobler, H. Analysis of the computational requirements of a pulse-doppler radar signal processor. 2012 IEEE Radar Conference, Atlanta, Georgia, USA, 7-11 May 2012, pp 0835-0840. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of CSIR Information Services' products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. en_US
dc.description.abstract In an attempt to find an optimal processing architecture for radar signal processing applications, the different algorithms that are typically used in a pulse-Doppler radar signal processor are investigated. Radar algorithms are broken down into mathematical operations and the relative processing requirements of each operation is determined. Implementation alternatives for the operations with the highest relative processing requirements are briefly discussed for an FPGA based soft-core architecture. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.relation.ispartofseries Workflow;8539
dc.subject RSP en_US
dc.subject Doppler processing en_US
dc.subject CFAR processing en_US
dc.subject Processing requirements en_US
dc.subject Computational requirements en_US
dc.subject Optimized architecture en_US
dc.title Analysis of the computational requirements of a pulse-doppler radar signal processor en_US
dc.type Conference Presentation en_US
dc.identifier.apacitation Broich, R., & Grobler, H. (2012). Analysis of the computational requirements of a pulse-doppler radar signal processor. IEEE. http://hdl.handle.net/10204/6008 en_ZA
dc.identifier.chicagocitation Broich, R, and H Grobler. "Analysis of the computational requirements of a pulse-doppler radar signal processor." (2012): http://hdl.handle.net/10204/6008 en_ZA
dc.identifier.vancouvercitation Broich R, Grobler H, Analysis of the computational requirements of a pulse-doppler radar signal processor; IEEE; 2012. http://hdl.handle.net/10204/6008 . en_ZA
dc.identifier.ris TY - Conference Presentation AU - Broich, R AU - Grobler, H AB - In an attempt to find an optimal processing architecture for radar signal processing applications, the different algorithms that are typically used in a pulse-Doppler radar signal processor are investigated. Radar algorithms are broken down into mathematical operations and the relative processing requirements of each operation is determined. Implementation alternatives for the operations with the highest relative processing requirements are briefly discussed for an FPGA based soft-core architecture. DA - 2012-05 DB - ResearchSpace DP - CSIR KW - RSP KW - Doppler processing KW - CFAR processing KW - Processing requirements KW - Computational requirements KW - Optimized architecture LK - https://researchspace.csir.co.za PY - 2012 SM - 978-1-4673-0656-0 T1 - Analysis of the computational requirements of a pulse-doppler radar signal processor TI - Analysis of the computational requirements of a pulse-doppler radar signal processor UR - http://hdl.handle.net/10204/6008 ER - en_ZA


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