Reddy, ReeshenSinha, S2016-12-082016-12-082015-04Reddy, R. and Sinha, S. 2015. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. Microelectronics Journal, 46(4), 310-3190026-2692http://www.sciencedirect.com/science/article/pii/S0026269215000257http://hdl.handle.net/10204/8886Copyright: 2016 Elsevier. Due to copyright restrictions, the attached PDF file only contains the abstract of the full text item. For access to the full text item, please consult the publisher's website. The definitive version of the work is published in Microelectronics Journal, 46(4),pp 310-319This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon¿germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.enBiCMOS integrated circuitsDynamic rangeAnalogue-digital integrated circuitsMixed analogue digital integrated circuitsWidebandDigital-to-analogue converterDACSpurious free dynamic rangeSFDRNegative-channel metal-oxide semiconductorNMOSArticleReddy, R., & Sinha, S. (2015). A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. http://hdl.handle.net/10204/8886Reddy, Reeshen, and S Sinha "A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance." (2015) http://hdl.handle.net/10204/8886Reddy R, Sinha S. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. 2015; http://hdl.handle.net/10204/8886.TY - Article AU - Reddy, Reeshen AU - Sinha, S AB - This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon¿germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation. DA - 2015-04 DB - ResearchSpace DP - CSIR KW - BiCMOS integrated circuits KW - Dynamic range KW - Analogue-digital integrated circuits KW - Mixed analogue digital integrated circuits KW - Wideband KW - Digital-to-analogue converter KW - DAC KW - Spurious free dynamic range KW - SFDR KW - Negative-channel metal-oxide semiconductor KW - NMOS LK - https://researchspace.csir.co.za PY - 2015 SM - 0026-2692 T1 - A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance TI - A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance UR - http://hdl.handle.net/10204/8886 ER -