Tsague, HDTwala, B2016-04-222016-04-222015-10Tsague, H.D and Twala, B. 2015. Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs. In: The 5th International Conference on Digital Information Processing and Communications (ICDIPC2015), 7-9 October 2015, Sierres, Switzerland978-1-4673-6832-2http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7323003&tag=1http://hdl.handle.net/10204/8515The 5th International Conference on Digital Information Processing and Communications (ICDIPC2015), 7-9 October 2015, Sierres, Switzerland. Due to copyright restrictions, the attached PDF file only contains the abstract of the full text item. For access to the full text item, please consult the publisher's websiteAlthough cryptography constitutes a considerable part of the overall security architecture for several use cases in embedded systems, cryptographic devices are still vulnerable to the diversity types of side channel attacks. Improvement in performance of Si-MOSFETs through conventional device scaling has become more difficult, because of several physical limitations associated with the device miniaturization. Thus, much attention has recently been paid to the mobility enhancement technology through applying strain to CMOS channels. This paper reviews the characteristics of strained-Si CMOS with an emphasis on the mechanism of mobility enhancement due to strain. The device physics for improving drive current of MOSFETs is summarized from the viewpoint of electronic states of carriers in inversion layers and, in particular, the sub-band structures. In addition, design and simulation of biaxial strained silicon NMOSFET (n-channel) is done using Silvaco’s Athena/Atlas simulator. From the results obtained, it became clear that biaxial strained silicon NMOS is one of the best alternatives to the current conventional MOSFET.enCryptographic keysEncryptionSide channelMOSFETBiaxialSiliconLeakage currentsSubthreshold voltageConference PresentationTsague, H., & Twala, B. (2015). Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs. IEEE. http://hdl.handle.net/10204/8515Tsague, HD, and B Twala. "Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs." (2015): http://hdl.handle.net/10204/8515Tsague H, Twala B, Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs; IEEE; 2015. http://hdl.handle.net/10204/8515 .TY - Conference Presentation AU - Tsague, HD AU - Twala, B AB - Although cryptography constitutes a considerable part of the overall security architecture for several use cases in embedded systems, cryptographic devices are still vulnerable to the diversity types of side channel attacks. Improvement in performance of Si-MOSFETs through conventional device scaling has become more difficult, because of several physical limitations associated with the device miniaturization. Thus, much attention has recently been paid to the mobility enhancement technology through applying strain to CMOS channels. This paper reviews the characteristics of strained-Si CMOS with an emphasis on the mechanism of mobility enhancement due to strain. The device physics for improving drive current of MOSFETs is summarized from the viewpoint of electronic states of carriers in inversion layers and, in particular, the sub-band structures. In addition, design and simulation of biaxial strained silicon NMOSFET (n-channel) is done using Silvaco’s Athena/Atlas simulator. From the results obtained, it became clear that biaxial strained silicon NMOS is one of the best alternatives to the current conventional MOSFET. DA - 2015-10 DB - ResearchSpace DP - CSIR KW - Cryptographic keys KW - Encryption KW - Side channel KW - MOSFET KW - Biaxial KW - Silicon KW - Leakage currents KW - Subthreshold voltage LK - https://researchspace.csir.co.za PY - 2015 SM - 978-1-4673-6832-2 T1 - Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs TI - Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs UR - http://hdl.handle.net/10204/8515 ER -