Frieslaar, IIrwin, B2017-01-172017-01-172016-07Frieslaar, I. and Irwin, B. 2016. Towards a software approach to mitigate correlation power analysis. Proceedings of the 13th International Joint Conference on e-Business and Telecommunications, 26-28 July 2016, Lisbon, Portugal.978-989-758-196-0http://www.scitepress.org/DigitalLibrary/PublicationsDetail.aspx?ID=ATREeXCX/YI=&t=1http://hdl.handle.net/10204/8912Proceedings of the 13th International Joint Conference on e-Business and Telecommunications, 26-28 July 2016, Lisbon, Portugal, pp 403-410.In this research we present a novel implementation for a software countermeasure to mitigate Correlation Power Analysis (CPA). This countermeasure combines pseudo controlled-random dummy code and a task scheduler using multi threads to form dynamic power traces which hides the occurrence of critical operations of the AES-128 algorithm. This work investigates the use of a task scheduler to generate noise at specific areas in the AES-128 algorithm to mitigate the CPA attack. The dynamic power traces have shown to be an effective contermeasure, as it obscures the CPA into predicting the incorrect secret key. Furthermore, the countermeasure is tested on an ATmega and an ATxmega microcontroller. The basic side channel analysis attack resistance has been increased and in both scenarios the countermeasure has reduced the correlation accuracy and forced the CPA to predict the incorect key. The correlation accuracy has decreased from 97.6% to 53.6% on the ATmega microntroller and from 82% to 51.4% on the ATxmega microcontroller.enSoftware CountermeasureTask SchedulerCorrelation Power AnalysisCPAData engineeringConference PresentationFrieslaar, I., & Irwin, B. (2016). Towards a software approach to mitigate correlation power analysis. SCITEPRESS Digital Library. http://hdl.handle.net/10204/8912Frieslaar, I, and B Irwin. "Towards a software approach to mitigate correlation power analysis." (2016): http://hdl.handle.net/10204/8912Frieslaar I, Irwin B, Towards a software approach to mitigate correlation power analysis; SCITEPRESS Digital Library; 2016. http://hdl.handle.net/10204/8912 .TY - Conference Presentation AU - Frieslaar, I AU - Irwin, B AB - In this research we present a novel implementation for a software countermeasure to mitigate Correlation Power Analysis (CPA). This countermeasure combines pseudo controlled-random dummy code and a task scheduler using multi threads to form dynamic power traces which hides the occurrence of critical operations of the AES-128 algorithm. This work investigates the use of a task scheduler to generate noise at specific areas in the AES-128 algorithm to mitigate the CPA attack. The dynamic power traces have shown to be an effective contermeasure, as it obscures the CPA into predicting the incorrect secret key. Furthermore, the countermeasure is tested on an ATmega and an ATxmega microcontroller. The basic side channel analysis attack resistance has been increased and in both scenarios the countermeasure has reduced the correlation accuracy and forced the CPA to predict the incorect key. The correlation accuracy has decreased from 97.6% to 53.6% on the ATmega microntroller and from 82% to 51.4% on the ATxmega microcontroller. DA - 2016-07 DB - ResearchSpace DP - CSIR KW - Software Countermeasure KW - Task Scheduler KW - Correlation Power Analysis KW - CPA KW - Data engineering LK - https://researchspace.csir.co.za PY - 2016 SM - 978-989-758-196-0 T1 - Towards a software approach to mitigate correlation power analysis TI - Towards a software approach to mitigate correlation power analysis UR - http://hdl.handle.net/10204/8912 ER -