Duvenhage, B2007-10-082007-10-082007-09Duvenhage, B. 2007. Migrating to a real-time distributed parallel simulator architecture-An update. South African Institute of Computer Scientists and Information Technologists Conference. Fish River Sun, Sunshine Coast, South Africa. 30 Sept - 3 Oct 2007, pp 6http://hdl.handle.net/10204/12892007: South African Institute of Computer Scientists and Information Technologists ConferenceA legacy non-distributed logical time simulator was previously migrated to a distributed architecture to parallelise execution. The existing Discrete Time System Specification (DTSS) modelling formalism was retained to simplify the reuse of existing models. This decision, however means that the high simulation frame rate of 100Hz used in the legacy system has to be retained in the distributed one-a known difficulty for existing distribution technologies due to inter- process communication latency. The specialised discrete time distributed peer-to-peer message passing architecture that resulted to support the parallelised simulator requirements is analysed and the questions surrounding its performance and exibility answered. The architecture is shown to be suitable and cost effective distributed simulator architecture for supporting a four to five times parallelised implementation of a 100 Hz logical time DTSS modelling formalism. From the analysis results it is however clear that the discrete time architecture poses a significant technical challenge in supporting large scale distributed parallel simulations. This is mainly due to sequential communication components within the discrete time architecture and system specification that cannot be parallelised. A hybrid DTSS/Discrete Event System Specification (DEVS) modelling formalism. and simulator is proposed to lower the communication and synchronisation overhead between models and improve on the scalability of the discrete time simulator while still economically reusing the existing models. The proposed hybrid architecture is discussed. Ideas on implementing and then analysing the new architecture to complete the author's master’s dissertation are then touched uponenDiscrete time system specificationDiscrete event simulationDistributed parallel simulationDEVSDiscrete event system specificationConference PresentationDuvenhage, B. (2007). Migrating to a real-time distributed parallel simulator architecture- An update. http://hdl.handle.net/10204/1289Duvenhage, B. "Migrating to a real-time distributed parallel simulator architecture- An update." (2007): http://hdl.handle.net/10204/1289Duvenhage B, Migrating to a real-time distributed parallel simulator architecture- An update; 2007. http://hdl.handle.net/10204/1289 .TY - Conference Presentation AU - Duvenhage, B AB - A legacy non-distributed logical time simulator was previously migrated to a distributed architecture to parallelise execution. The existing Discrete Time System Specification (DTSS) modelling formalism was retained to simplify the reuse of existing models. This decision, however means that the high simulation frame rate of 100Hz used in the legacy system has to be retained in the distributed one-a known difficulty for existing distribution technologies due to inter- process communication latency. The specialised discrete time distributed peer-to-peer message passing architecture that resulted to support the parallelised simulator requirements is analysed and the questions surrounding its performance and exibility answered. The architecture is shown to be suitable and cost effective distributed simulator architecture for supporting a four to five times parallelised implementation of a 100 Hz logical time DTSS modelling formalism. From the analysis results it is however clear that the discrete time architecture poses a significant technical challenge in supporting large scale distributed parallel simulations. This is mainly due to sequential communication components within the discrete time architecture and system specification that cannot be parallelised. A hybrid DTSS/Discrete Event System Specification (DEVS) modelling formalism. and simulator is proposed to lower the communication and synchronisation overhead between models and improve on the scalability of the discrete time simulator while still economically reusing the existing models. The proposed hybrid architecture is discussed. Ideas on implementing and then analysing the new architecture to complete the author's master’s dissertation are then touched upon DA - 2007-09 DB - ResearchSpace DP - CSIR KW - Discrete time system specification KW - Discrete event simulation KW - Distributed parallel simulation KW - DEVS KW - Discrete event system specification LK - https://researchspace.csir.co.za PY - 2007 T1 - Migrating to a real-time distributed parallel simulator architecture- An update TI - Migrating to a real-time distributed parallel simulator architecture- An update UR - http://hdl.handle.net/10204/1289 ER -