dc.contributor.author |
Reddy, Reeshen
|
|
dc.contributor.author |
Sinha, S
|
|
dc.date.accessioned |
2016-12-08T07:42:35Z |
|
dc.date.available |
2016-12-08T07:42:35Z |
|
dc.date.issued |
2015-04 |
|
dc.identifier.citation |
Reddy, R. and Sinha, S. 2015. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. Microelectronics Journal, 46(4), 310-319 |
en_US |
dc.identifier.issn |
0026-2692 |
|
dc.identifier.uri |
http://www.sciencedirect.com/science/article/pii/S0026269215000257
|
|
dc.identifier.uri |
http://hdl.handle.net/10204/8886
|
|
dc.description |
Copyright: 2016 Elsevier. Due to copyright restrictions, the attached PDF file only contains the abstract of the full text item. For access to the full text item, please consult the publisher's website. The definitive version of the work is published in Microelectronics Journal, 46(4),pp 310-319 |
en_US |
dc.description.abstract |
This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon¿germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Elsevier |
en_US |
dc.relation.ispartofseries |
Wokflow;16311 |
|
dc.subject |
BiCMOS integrated circuits |
en_US |
dc.subject |
Dynamic range |
en_US |
dc.subject |
Analogue-digital integrated circuits |
en_US |
dc.subject |
Mixed analogue digital integrated circuits |
en_US |
dc.subject |
Wideband |
en_US |
dc.subject |
Digital-to-analogue converter |
en_US |
dc.subject |
DAC |
en_US |
dc.subject |
Spurious free dynamic range |
en_US |
dc.subject |
SFDR |
en_US |
dc.subject |
Negative-channel metal-oxide semiconductor |
en_US |
dc.subject |
NMOS |
en_US |
dc.title |
A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance |
en_US |
dc.type |
Article |
en_US |
dc.identifier.apacitation |
Reddy, R., & Sinha, S. (2015). A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. http://hdl.handle.net/10204/8886 |
en_ZA |
dc.identifier.chicagocitation |
Reddy, Reeshen, and S Sinha "A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance." (2015) http://hdl.handle.net/10204/8886 |
en_ZA |
dc.identifier.vancouvercitation |
Reddy R, Sinha S. A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance. 2015; http://hdl.handle.net/10204/8886. |
en_ZA |
dc.identifier.ris |
TY - Article
AU - Reddy, Reeshen
AU - Sinha, S
AB - This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon¿germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.
DA - 2015-04
DB - ResearchSpace
DP - CSIR
KW - BiCMOS integrated circuits
KW - Dynamic range
KW - Analogue-digital integrated circuits
KW - Mixed analogue digital integrated circuits
KW - Wideband
KW - Digital-to-analogue converter
KW - DAC
KW - Spurious free dynamic range
KW - SFDR
KW - Negative-channel metal-oxide semiconductor
KW - NMOS
LK - https://researchspace.csir.co.za
PY - 2015
SM - 0026-2692
T1 - A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance
TI - A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance
UR - http://hdl.handle.net/10204/8886
ER -
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en_ZA |