The design, fabrication and preliminary testing of a chipscale, multi-zone, surface electrode ion trap is reported. The modular design and fabrication techniques used are anticipated to advance scalability of ion trap quantum computing architectures
Reference:
Uys, H, Amini, JM, Wesenberg, JH et al. 2010. Scaling ion traps for quantum computing. 55th Annual Conference of the South African Institute of Physics (SAIP), CSIR International Convention Centre, Pretoria, 27 September-1 October 2010
Uys, H., Amini, J., Wesenberg, J., Seidelin, S., Britton, J., Bollinger, J., ... Wineland, D. (2010). Scaling ion traps for quantum computing. SAIP 2010. http://hdl.handle.net/10204/4785
Uys, H, JM Amini, JH Wesenberg, S Seidelin, J Britton, JJ Bollinger, D Leibfried, C Ospelkaus, AP Van Deventer, and DJ Wineland. "Scaling ion traps for quantum computing." (2010): http://hdl.handle.net/10204/4785
Uys H, Amini J, Wesenberg J, Seidelin S, Britton J, Bollinger J, et al, Scaling ion traps for quantum computing; SAIP 2010; 2010. http://hdl.handle.net/10204/4785 .
